Reality Labs ASIC Engineering Manager, Design Verification

Sunnyvale, California

Posted in Retail

Job Info

The ideal candidate will be a consensus driven leader with management and leadership experience in small to large size organizations, with comprehensive system and silicon development experience, and a proven track record of first-pass success in ASIC and Systems.

Reality Labs ASIC Engineering Manager, Design Verification Responsibilities:

  • Manage an ASIC design verification team responsible for various pervasive IPs in an SOC
  • Drive verification planning and execution, innovative verification methodology development, functional and code coverage closure
  • Participate in silicon architecture, micro-architecture development, interface with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation teams
  • Collaborate with IP development teams for integration of pervasive IPs into their design
  • Partner with SoC and IP architects to drive roadmaps for future designs
  • Support organization wide initiatives on improving design and verification methodologies
  • Define, implement and maintain key performance indicators (KPI) for areas of responsibility
  • Partner with technical program management to communicate status, issues and project updates
  • Identify candidates, hire, support and train a team of ASIC engineers in order to develop products on time

Minimum Qualifications:

  • B.S/M.S/Ph.D. degree in Computer Engineering or Electrical Engineering
  • 5+ years technical leadership experience managing digital design/verification teams
  • Track record of first-pass success in ASIC Development
  • Experience working across multiple projects and adjusting priorities in partnership with stakeholders
  • Experience managing and delivering SV/UVM constrained random test benches
  • Experience with interpreting functional specs and creating comprehensive test plan
  • Clear understanding of complexities involved with various design verification tools, including Synopsys VCS or Cadence Xcelium simulator, Verdi, JasperGold or VC Formal

Preferred Qualifications:

  • Chip-level architecture, µArchitecture, design and design verification experience
  • Experience designing of on-chip power controllers
  • Deep understanding of on-chip interface protocols (ARM AMBA, OCP)
  • Capable of dealing with ambiguity in a fast changing consumer electronics field
  • Results oriented, self-motivated, proactive with demonstrated creative & critical thinking skills
  • Skilled in design and verification using SystemVerilog/UVM and automation languages such as Python

Facebook is proud to be an Equal Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law.Facebook is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at

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